Lab notes

• Aug 30, 2021 : Quartus Setup
• Sep 13, 2021 : Verilog and Multiplexers
• Sep 20, 2021 : Verilog Modules
• Sep 27, 2021 : Ripple Adder
• Oct 18, 2021 : Logic Synthesis and Always Blocks
• Oct 25, 2021 : Procedural Verilog and Binary to BCD
• Nov 1, 2021 : Verilog Code Quality
• Nov 15, 2021 : HDL Simulation

Lab supporting documents

• Pin Assignments : DE0_TOP.qsf
• DE0 FPGA Manual : DEO User Manual

Prelabs

• Prelab for Lab 5 : Lab 5 Prelab

Additional Resources

• Intel/Altera Document on Synthesis of Math Functions : Advanced Synthesis Cookbook

VGA Driver Files

• VGA Video Tutorial (Must be logged in to you Umaine account to view) : Video Tutorial
  • There is a mistake in the video when instantiating the make box module, it should be make_box make_first_player_paddle( and not module make_first_player make_box(
• Example simple top level : VGA_top.v
• DE0 VGA Driver Module : DE0_VGA.v
• PLL (Phase Locked Loop) Verilog File : PLL_PIXEL_CLK.v
• QSF File : VGA_top.qsf

Testbenches

• Tutorial video on testbenches (Must be logged in to you Umaine account to view) : Testbenches Tutorial